Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier

<span lang="EN-US">In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It always challenging task to design the delay optimized at system level. A new and delay-efficient structure for 4:3 counter proposed by making use of two-bit reordering circuit. The along with 7:3 counter, full adder (FA), half (HA) circuits are employed 8-bit 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, designed simulated synthesized targeting device ‘xc7s50fgga484-1’ Spartan 7 family. Further, terms lookup table (LUT) count, critical path (CPD), total on-chip power, power-delay-product (PDP), performance circuit compared existing multipliers.</span>